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usr /
src /
linux-headers-5.15.0-25 /
include /
linux /
[ HOME SHELL ]
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amba
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drwxr-xr-x
atomic
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drwxr-xr-x
avf
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drwxr-xr-x
bcma
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drwxr-xr-x
byteorder
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drwxr-xr-x
can
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drwxr-xr-x
ceph
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drwxr-xr-x
clk
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drwxr-xr-x
crush
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decompress
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device
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dma
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dsa
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fsl
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hsi
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input
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irqchip
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isdn
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lockd
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mfd
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mlx4
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mmc
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mtd
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mux
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net
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netfilter
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netfilter_arp
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netfilter_bridge
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drwxr-xr-x
netfilter_ipv4
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netfilter_ipv6
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pcs
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perf
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phy
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pinctrl
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platform_data
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power
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qed
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raid
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regulator
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remoteproc
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drwxr-xr-x
reset
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rpmsg
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rtc
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sched
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drwxr-xr-x
soc
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soundwire
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drwxr-xr-x
spi
[ DIR ]
drwxr-xr-x
ssb
[ DIR ]
drwxr-xr-x
sunrpc
[ DIR ]
drwxr-xr-x
surface_aggregator
[ DIR ]
drwxr-xr-x
ulpi
[ DIR ]
drwxr-xr-x
unaligned
[ DIR ]
drwxr-xr-x
usb
[ DIR ]
drwxr-xr-x
8250_pci.h
1.01
KB
-rw-r--r--
a.out.h
354
B
-rw-r--r--
acct.h
2.49
KB
-rw-r--r--
acpi.h
39.5
KB
-rw-r--r--
acpi_dma.h
3.08
KB
-rw-r--r--
acpi_iort.h
2.27
KB
-rw-r--r--
acpi_mdio.h
631
B
-rw-r--r--
acpi_pmtmr.h
674
B
-rw-r--r--
acpi_viot.h
389
B
-rw-r--r--
adb.h
1.79
KB
-rw-r--r--
adfs_fs.h
574
B
-rw-r--r--
adreno-smmu-priv.h
2.74
KB
-rw-r--r--
adxl.h
310
B
-rw-r--r--
aer.h
1.78
KB
-rw-r--r--
agp_backend.h
3.45
KB
-rw-r--r--
agpgart.h
3.79
KB
-rw-r--r--
ahci-remap.h
607
B
-rw-r--r--
ahci_platform.h
1.54
KB
-rw-r--r--
aio.h
651
B
-rw-r--r--
alarmtimer.h
1.94
KB
-rw-r--r--
alcor_pci.h
8.83
KB
-rw-r--r--
align.h
552
B
-rw-r--r--
altera_jtaguart.h
379
B
-rw-r--r--
altera_uart.h
397
B
-rw-r--r--
amd-iommu.h
6.18
KB
-rw-r--r--
anon_inodes.h
670
B
-rw-r--r--
apm-emulation.h
1.56
KB
-rw-r--r--
apm_bios.h
2.25
KB
-rw-r--r--
apple-gmux.h
918
B
-rw-r--r--
apple_bl.h
498
B
-rw-r--r--
arch_topology.h
2.49
KB
-rw-r--r--
arm-cci.h
1.36
KB
-rw-r--r--
arm-smccc.h
17.7
KB
-rw-r--r--
arm_ffa.h
7.36
KB
-rw-r--r--
arm_sdei.h
2.51
KB
-rw-r--r--
armada-37xx-rwtm-mailbox.h
431
B
-rw-r--r--
ascii85.h
555
B
-rw-r--r--
asn1.h
1.79
KB
-rw-r--r--
asn1_ber_bytecode.h
2.52
KB
-rw-r--r--
asn1_decoder.h
468
B
-rw-r--r--
asn1_encoder.h
1006
B
-rw-r--r--
assoc_array.h
2.88
KB
-rw-r--r--
assoc_array_priv.h
5.3
KB
-rw-r--r--
async.h
4.26
KB
-rw-r--r--
async_tx.h
6.7
KB
-rw-r--r--
ata.h
32.52
KB
-rw-r--r--
ata_platform.h
749
B
-rw-r--r--
atalk.h
4.48
KB
-rw-r--r--
ath9k_platform.h
1.44
KB
-rw-r--r--
atm.h
287
B
-rw-r--r--
atm_tcp.h
511
B
-rw-r--r--
atmdev.h
9.99
KB
-rw-r--r--
atmel-isc-media.h
2.07
KB
-rw-r--r--
atmel-mci.h
1.4
KB
-rw-r--r--
atmel-ssc.h
9.74
KB
-rw-r--r--
atmel_pdc.h
1.26
KB
-rw-r--r--
atomic.h
2.58
KB
-rw-r--r--
attribute_container.h
2.74
KB
-rw-r--r--
audit.h
19.45
KB
-rw-r--r--
auto_dev-ioctl.h
296
B
-rw-r--r--
auto_fs.h
278
B
-rw-r--r--
auxiliary_bus.h
2.48
KB
-rw-r--r--
auxvec.h
304
B
-rw-r--r--
average.h
2.42
KB
-rw-r--r--
backing-dev-defs.h
8.55
KB
-rw-r--r--
backing-dev.h
11.81
KB
-rw-r--r--
backlight.h
13.13
KB
-rw-r--r--
badblocks.h
2.14
KB
-rw-r--r--
balloon_compaction.h
6.59
KB
-rw-r--r--
bcd.h
559
B
-rw-r--r--
bch.h
2.1
KB
-rw-r--r--
bcm47xx_nvram.h
1.01
KB
-rw-r--r--
bcm47xx_sprom.h
616
B
-rw-r--r--
bcm47xx_wdt.h
555
B
-rw-r--r--
bcm963xx_nvram.h
2.96
KB
-rw-r--r--
bcm963xx_tag.h
3.6
KB
-rw-r--r--
binfmts.h
4.48
KB
-rw-r--r--
bio.h
19.64
KB
-rw-r--r--
bit_spinlock.h
2.3
KB
-rw-r--r--
bitfield.h
4.75
KB
-rw-r--r--
bitmap.h
21.62
KB
-rw-r--r--
bitops.h
8.53
KB
-rw-r--r--
bitrev.h
2.53
KB
-rw-r--r--
bits.h
1.35
KB
-rw-r--r--
blk-cgroup.h
21.4
KB
-rw-r--r--
blk-crypto.h
4.02
KB
-rw-r--r--
blk-mq-pci.h
269
B
-rw-r--r--
blk-mq-rdma.h
273
B
-rw-r--r--
blk-mq-virtio.h
293
B
-rw-r--r--
blk-mq.h
19.37
KB
-rw-r--r--
blk-pm.h
708
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-rw-r--r--
blk_types.h
15.42
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-rw-r--r--
blkdev.h
56.35
KB
-rw-r--r--
blkpg.h
436
B
-rw-r--r--
blktrace_api.h
3.77
KB
-rw-r--r--
blockgroup_lock.h
810
B
-rw-r--r--
bma150.h
1.26
KB
-rw-r--r--
bootconfig.h
8.51
KB
-rw-r--r--
bootmem_info.h
1.61
KB
-rw-r--r--
bottom_half.h
974
B
-rw-r--r--
bpf-cgroup.h
18.52
KB
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bpf-netns.h
1.52
KB
-rw-r--r--
bpf.h
69.46
KB
-rw-r--r--
bpf_lirc.h
698
B
-rw-r--r--
bpf_local_storage.h
5.23
KB
-rw-r--r--
bpf_lsm.h
1.42
KB
-rw-r--r--
bpf_trace.h
166
B
-rw-r--r--
bpf_types.h
5.41
KB
-rw-r--r--
bpf_verifier.h
18.45
KB
-rw-r--r--
bpfilter.h
791
B
-rw-r--r--
bpfptr.h
1.83
KB
-rw-r--r--
brcmphy.h
13.67
KB
-rw-r--r--
bsearch.h
624
B
-rw-r--r--
bsg-lib.h
1.72
KB
-rw-r--r--
bsg.h
492
B
-rw-r--r--
btf.h
7.26
KB
-rw-r--r--
btf_ids.h
5.32
KB
-rw-r--r--
btree-128.h
2.67
KB
-rw-r--r--
btree-type.h
3.9
KB
-rw-r--r--
btree.h
6.84
KB
-rw-r--r--
btrfs.h
145
B
-rw-r--r--
buffer_head.h
13.54
KB
-rw-r--r--
bug.h
2.17
KB
-rw-r--r--
build-salt.h
375
B
-rw-r--r--
build_bug.h
2.76
KB
-rw-r--r--
buildid.h
561
B
-rw-r--r--
bvec.h
6.17
KB
-rw-r--r--
c2port.h
1.35
KB
-rw-r--r--
cache.h
2.55
KB
-rw-r--r--
cacheinfo.h
3.75
KB
-rw-r--r--
capability.h
8.29
KB
-rw-r--r--
cb710.h
5.36
KB
-rw-r--r--
cc_platform.h
2.32
KB
-rw-r--r--
cciss_ioctl.h
1.03
KB
-rw-r--r--
ccp.h
18.14
KB
-rw-r--r--
cdev.h
845
B
-rw-r--r--
cdrom.h
8.98
KB
-rw-r--r--
cfag12864b.h
1.47
KB
-rw-r--r--
cfi.h
1.13
KB
-rw-r--r--
cgroup-defs.h
24.1
KB
-rw-r--r--
cgroup.h
28.19
KB
-rw-r--r--
cgroup_rdma.h
1.18
KB
-rw-r--r--
cgroup_subsys.h
1.23
KB
-rw-r--r--
circ_buf.h
1.09
KB
-rw-r--r--
cleancache.h
3.89
KB
-rw-r--r--
clk-provider.h
56.38
KB
-rw-r--r--
clk.h
29.59
KB
-rw-r--r--
clkdev.h
1.29
KB
-rw-r--r--
clockchips.h
7.27
KB
-rw-r--r--
clocksource.h
9.57
KB
-rw-r--r--
clocksource_ids.h
247
B
-rw-r--r--
cm4000_cs.h
199
B
-rw-r--r--
cma.h
1.59
KB
-rw-r--r--
cn_proc.h
1.85
KB
-rw-r--r--
cnt32_to_63.h
3.46
KB
-rw-r--r--
coda.h
2.16
KB
-rw-r--r--
compaction.h
7.15
KB
-rw-r--r--
compat.h
31.35
KB
-rw-r--r--
compiler-clang.h
2.27
KB
-rw-r--r--
compiler-gcc.h
4.44
KB
-rw-r--r--
compiler-intel.h
949
B
-rw-r--r--
compiler-version.h
517
B
-rw-r--r--
compiler.h
7.78
KB
-rw-r--r--
compiler_attributes.h
12.15
KB
-rw-r--r--
compiler_types.h
10.46
KB
-rw-r--r--
completion.h
4
KB
-rw-r--r--
component.h
4.07
KB
-rw-r--r--
configfs.h
8.48
KB
-rw-r--r--
connector.h
3.83
KB
-rw-r--r--
console.h
7.28
KB
-rw-r--r--
console_struct.h
7.08
KB
-rw-r--r--
consolemap.h
1.05
KB
-rw-r--r--
const.h
421
B
-rw-r--r--
container.h
610
B
-rw-r--r--
context_tracking.h
3.28
KB
-rw-r--r--
context_tracking_state.h
1.58
KB
-rw-r--r--
cookie.h
1.22
KB
-rw-r--r--
cordic.h
2.08
KB
-rw-r--r--
coredump.h
1.23
KB
-rw-r--r--
coresight-pmu.h
1.32
KB
-rw-r--r--
coresight-stm.h
152
B
-rw-r--r--
coresight.h
17.81
KB
-rw-r--r--
count_zeros.h
1.42
KB
-rw-r--r--
counter.h
15.13
KB
-rw-r--r--
counter_enum.h
1.43
KB
-rw-r--r--
cper.h
16.41
KB
-rw-r--r--
cpu.h
7.31
KB
-rw-r--r--
cpu_cooling.h
1.86
KB
-rw-r--r--
cpu_pm.h
2.38
KB
-rw-r--r--
cpu_rmap.h
1.68
KB
-rw-r--r--
cpufeature.h
1.71
KB
-rw-r--r--
cpufreq.h
32.57
KB
-rw-r--r--
cpuhotplug.h
16.47
KB
-rw-r--r--
cpuidle.h
10.27
KB
-rw-r--r--
cpuidle_haltpoll.h
312
B
-rw-r--r--
cpumask.h
28.61
KB
-rw-r--r--
cpuset.h
7.34
KB
-rw-r--r--
crash_core.h
3.38
KB
-rw-r--r--
crash_dump.h
4.05
KB
-rw-r--r--
crc-ccitt.h
609
B
-rw-r--r--
crc-itu-t.h
531
B
-rw-r--r--
crc-t10dif.h
453
B
-rw-r--r--
crc16.h
540
B
-rw-r--r--
crc32.h
2.83
KB
-rw-r--r--
crc32c.h
331
B
-rw-r--r--
crc32poly.h
610
B
-rw-r--r--
crc4.h
192
B
-rw-r--r--
crc64.h
280
B
-rw-r--r--
crc7.h
316
B
-rw-r--r--
crc8.h
3.66
KB
-rw-r--r--
cred.h
12.48
KB
-rw-r--r--
crypto.h
27.08
KB
-rw-r--r--
cs5535.h
6.13
KB
-rw-r--r--
ctype.h
1.87
KB
-rw-r--r--
cuda.h
613
B
-rw-r--r--
damon.h
10.35
KB
-rw-r--r--
dasd_mod.h
204
B
-rw-r--r--
davinci_emac.h
1.05
KB
-rw-r--r--
dax.h
6.56
KB
-rw-r--r--
dca.h
1.88
KB
-rw-r--r--
dcache.h
18.63
KB
-rw-r--r--
dccp.h
10.73
KB
-rw-r--r--
debug_locks.h
1.59
KB
-rw-r--r--
debugfs.h
11.22
KB
-rw-r--r--
debugobjects.h
3.99
KB
-rw-r--r--
delay.h
2.43
KB
-rw-r--r--
delayacct.h
5.45
KB
-rw-r--r--
delayed_call.h
709
B
-rw-r--r--
dev_printk.h
9.05
KB
-rw-r--r--
devcoredump.h
2.21
KB
-rw-r--r--
devfreq-event.h
5.95
KB
-rw-r--r--
devfreq.h
13.98
KB
-rw-r--r--
devfreq_cooling.h
2.7
KB
-rw-r--r--
device-mapper.h
18.92
KB
-rw-r--r--
device.h
32.89
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-rw-r--r--
device_cgroup.h
1.57
KB
-rw-r--r--
devm-helpers.h
2.68
KB
-rw-r--r--
devpts_fs.h
1.13
KB
-rw-r--r--
dfl.h
2.38
KB
-rw-r--r--
digsig.h
1.18
KB
-rw-r--r--
dim.h
9.13
KB
-rw-r--r--
dio.h
10.76
KB
-rw-r--r--
dirent.h
215
B
-rw-r--r--
dlm.h
5.86
KB
-rw-r--r--
dlm_plock.h
532
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-rw-r--r--
dm-bufio.h
4.88
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-rw-r--r--
dm-dirty-log.h
3.94
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-rw-r--r--
dm-io.h
1.93
KB
-rw-r--r--
dm-kcopyd.h
2.94
KB
-rw-r--r--
dm-region-hash.h
3.11
KB
-rw-r--r--
dm9000.h
987
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-rw-r--r--
dma-buf-map.h
8.12
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-rw-r--r--
dma-buf.h
20.47
KB
-rw-r--r--
dma-direct.h
3.59
KB
-rw-r--r--
dma-direction.h
407
B
-rw-r--r--
dma-fence-array.h
2.14
KB
-rw-r--r--
dma-fence-chain.h
3.07
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-rw-r--r--
dma-fence.h
20.25
KB
-rw-r--r--
dma-heap.h
1.58
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-rw-r--r--
dma-iommu.h
2.21
KB
-rw-r--r--
dma-map-ops.h
12.73
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-rw-r--r--
dma-mapping.h
19.81
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-rw-r--r--
dma-resv.h
9.05
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-rw-r--r--
dmaengine.h
53.53
KB
-rw-r--r--
dmapool.h
1.79
KB
-rw-r--r--
dmar.h
7.74
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-rw-r--r--
dmi.h
4.27
KB
-rw-r--r--
dnotify.h
1.02
KB
-rw-r--r--
dns_resolver.h
1.36
KB
-rw-r--r--
dqblk_qtree.h
2.19
KB
-rw-r--r--
dqblk_v1.h
327
B
-rw-r--r--
dqblk_v2.h
406
B
-rw-r--r--
drbd.h
10.07
KB
-rw-r--r--
drbd_genl.h
21.49
KB
-rw-r--r--
drbd_genl_api.h
1.77
KB
-rw-r--r--
drbd_limits.h
7.82
KB
-rw-r--r--
ds2782_battery.h
158
B
-rw-r--r--
dtlk.h
3.5
KB
-rw-r--r--
dtpm.h
1.64
KB
-rw-r--r--
dw_apb_timer.h
1.53
KB
-rw-r--r--
dynamic_debug.h
6.6
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elevator.h
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elf-fdpic.h
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elf-randomize.h
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elfcore-compat.h
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elfcore.h
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energy_model.h
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errseq.h
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etherdevice.h
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ethtool.h
31.72
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ethtool_netlink.h
1.98
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eventfd.h
2.1
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eventpoll.h
2.4
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evm.h
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export.h
5.24
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exportfs.h
8.25
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ext2_fs.h
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extable.h
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extcon-provider.h
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extcon.h
10.17
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f2fs_fs.h
19
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fanotify.h
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fault-inject-usercopy.h
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fault-inject.h
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fb.h
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fbcon.h
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833
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fileattr.h
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fips.h
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firewire.h
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firmware-map.h
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firmware.h
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fixp-arith.h
4.19
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flat.h
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font.h
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fortify-string.h
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freelist.h
3.8
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freezer.h
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frontswap.h
3.04
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fs.h
120.45
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fs_context.h
8.68
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fs_enet_pd.h
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fs_parser.h
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fs_stack.h
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629
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fsl-diu-fb.h
3.87
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fsl_devices.h
4.16
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fsl_hypervisor.h
2.76
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fsnotify.h
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fsnotify_backend.h
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fsverity.h
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ftrace_irq.h
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gameport.h
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genalloc.h
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generic-radix-tree.h
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genetlink.h
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genhd.h
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genl_magic_func.h
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genl_magic_struct.h
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getcpu.h
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gfp.h
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glob.h
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gnss.h
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goldfish.h
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gpio-pxa.h
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gpio.h
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gpio_keys.h
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greybus.h
4.14
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hardirq.h
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hash.h
3
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hashtable.h
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hdlc.h
3.19
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hdlcdrv.h
6.32
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hdmi.h
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hid-debug.h
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hid-roccat.h
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hidden.h
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hiddev.h
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highmem.h
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highuid.h
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hil_mlc.h
5.13
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hippidevice.h
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hmm.h
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host1x.h
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hp_sdc.h
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hpet.h
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hrtimer_defs.h
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htcpld.h
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huge_mm.h
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hugetlb.h
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hugetlb_cgroup.h
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hugetlb_inline.h
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hw_breakpoint.h
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hw_random.h
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hwmon-sysfs.h
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hwmon-vid.h
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hwmon.h
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hwspinlock.h
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hyperv.h
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hypervisor.h
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i2c-algo-bit.h
1.4
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icmp.h
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icmpv6.h
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idle_inject.h
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idr.h
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ieee80211.h
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ieee802154.h
11.12
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if_arp.h
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if_bridge.h
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if_eql.h
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if_ether.h
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if_fddi.h
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if_hsr.h
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if_ltalk.h
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if_tunnel.h
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if_vlan.h
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igmp.h
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ihex.h
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ima.h
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imx-media.h
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in6.h
1.63
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indirect_call_wrapper.h
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inet.h
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inet_diag.h
2.74
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inetdevice.h
8.87
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init.h
11.39
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init_ohci1394_dma.h
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init_syscalls.h
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init_task.h
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initrd.h
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inotify.h
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input.h
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instrumentation.h
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instrumented.h
3.6
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integrity.h
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intel-iommu.h
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intel-ish-client-if.h
3.97
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intel-svm.h
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intel_rapl.h
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intel_th.h
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interconnect-provider.h
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interconnect.h
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interrupt.h
23.81
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interval_tree.h
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interval_tree_generic.h
6.7
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io-64-nonatomic-lo-hi.h
2.41
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io-mapping.h
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io-pgtable.h
8.39
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io.h
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io_uring.h
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226
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ioam6_genl.h
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ioam6_iptunnel.h
285
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iocontext.h
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iomap.h
11.67
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iommu-helper.h
1.12
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iommu.h
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iopoll.h
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ioport.h
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ioprio.h
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iova.h
6.15
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ip.h
1
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ipack.h
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ipc.h
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ipc_namespace.h
4.98
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ipmi.h
10.88
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ipmi_smi.h
7.98
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ipv6.h
8.67
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ipv6_route.h
372
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irq.h
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irq_poll.h
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irq_sim.h
789
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irq_work.h
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irqbypass.h
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irqchip.h
2.33
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irqdesc.h
7.75
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irqdomain.h
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irqflags.h
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irqhandler.h
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irqnr.h
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irqreturn.h
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isapnp.h
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iscsi_boot_sysfs.h
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iscsi_ibft.h
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iversion.h
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jbd2.h
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jhash.h
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jiffies.h
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journal-head.h
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joystick.h
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jump_label.h
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jump_label_ratelimit.h
2.77
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jz4740-adc.h
1023
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jz4780-nemc.h
976
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kallsyms.h
4.5
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kasan-checks.h
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kasan-tags.h
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kasan.h
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kbd_diacr.h
198
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kbd_kern.h
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kbuild.h
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kconfig.h
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kcore.h
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kcov.h
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1.88
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kdb.h
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kdebug.h
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kdev_t.h
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kern_levels.h
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kernel-page-flags.h
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kernel.h
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kernel_read_file.h
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kernel_stat.h
2.97
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kernelcapi.h
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kernfs.h
18.11
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kexec.h
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key-type.h
6.53
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key.h
15.75
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keyboard.h
665
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keyctl.h
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keyslot-manager.h
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kfence.h
8
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kfifo.h
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kgdb.h
12.05
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khugepaged.h
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klist.h
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kmemleak.h
3.27
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kmsg_dump.h
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kobj_map.h
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kobject.h
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kobject_ns.h
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kprobes.h
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472
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kthread.h
6.9
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ktime.h
5.38
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kvm_dirty_ring.h
2.73
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kvm_host.h
58.09
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kvm_irqfd.h
2
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kvm_para.h
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kvm_types.h
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l2tp.h
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lantiq.h
365
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lapb.h
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latencytop.h
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lcd.h
3.78
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lcm.h
275
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led-class-flash.h
6.74
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led-class-multicolor.h
3.26
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led-lm3530.h
3.7
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leds-bd2802.h
476
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leds-lp3944.h
950
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leds-lp3952.h
2.35
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leds-pca9532.h
866
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leds-regulator.h
1.14
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leds-ti-lmu-common.h
1.12
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leds.h
18.26
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libata.h
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qcom_scm.h
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radix-tree.h
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raid_class.h
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ramfs.h
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random.h
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rcu_segcblist.h
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rcu_sync.h
1.46
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rculist.h
28.56
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rculist_bl.h
3.29
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rculist_nulls.h
6.57
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rcupdate.h
36.33
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rcupdate_trace.h
3.08
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rcupdate_wait.h
1.73
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rcutiny.h
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rcutree.h
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rcuwait.h
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reboot-mode.h
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reboot.h
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reciprocal_div.h
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refcount.h
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regmap.h
62.95
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regset.h
11.35
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relay.h
8.47
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remoteproc.h
24.77
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resctrl.h
6.5
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reset-controller.h
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reset.h
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resource_ext.h
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restart_block.h
1.11
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rfkill.h
10.52
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3.45
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rhashtable.h
37.59
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ring_buffer.h
7.43
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rio.h
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rio_drv.h
14.32
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rio_ids.h
1.08
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rio_regs.h
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rmap.h
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rmi.h
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rodata_test.h
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root_dev.h
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rpmsg.h
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rslib.h
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rtmutex.h
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rtnetlink.h
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rtsx_common.h
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rtsx_pci.h
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rtsx_usb.h
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rwbase_rt.h
876
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rwlock.h
4.55
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rwlock_api_smp.h
7.65
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rwlock_rt.h
2.98
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rwlock_types.h
1.77
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rwsem.h
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s3c_adc_battery.h
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scc.h
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sched.h
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sched_clock.h
1.44
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scmi_protocol.h
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scpi_protocol.h
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screen_info.h
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scs.h
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scx200.h
1.82
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scx200_gpio.h
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sdb.h
4.17
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seccomp.h
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secretmem.h
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securebits.h
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security.h
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sed-opal.h
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seg6.h
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seg6_genl.h
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seg6_local.h
100
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selection.h
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sem.h
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semaphore.h
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seq_buf.h
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seq_file.h
8.75
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seq_file_net.h
730
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seqlock.h
38.18
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seqno-fence.h
3.57
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serdev.h
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serial.h
630
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serial_8250.h
6.57
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serial_bcm63xx.h
4.73
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serial_core.h
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serial_max3100.h
1.19
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serial_s3c.h
9.42
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serial_sci.h
1.6
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serio.h
4.28
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set_memory.h
1.66
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sfp.h
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sh_clk.h
5.96
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sh_dma.h
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sh_eth.h
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shdma-base.h
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shm.h
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shmem_fs.h
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shrinker.h
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signal.h
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signal_types.h
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signalfd.h
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siox.h
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siphash.h
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sizes.h
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skb_array.h
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skbuff.h
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skmsg.h
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slab_def.h
3.02
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slimbus.h
6.93
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slub_def.h
6.22
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sm501-regs.h
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sm501.h
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smc911x.h
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smc91x.h
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smp.h
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smp_types.h
1.35
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smpboot.h
1.68
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smscphy.h
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sock_diag.h
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socket.h
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sockptr.h
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sonet.h
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sony-laptop.h
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sonypi.h
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sort.h
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sound.h
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soundcard.h
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spinlock.h
14.07
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spinlock_api_smp.h
5.47
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spinlock_api_up.h
3.31
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spinlock_rt.h
4.11
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spinlock_types.h
1.78
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spinlock_types_raw.h
1.69
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spinlock_types_up.h
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spinlock_up.h
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splice.h
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spmi.h
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sram.h
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srcu.h
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srcutiny.h
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srcutree.h
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ssbi.h
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stackdepot.h
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stackprotector.h
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statfs.h
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static_call_types.h
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static_key.h
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stddef.h
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stmmac.h
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stmp3xxx_rtc_wdt.h
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stmp_device.h
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stop_machine.h
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string.h
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string_helpers.h
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stringhash.h
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stringify.h
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sungem_phy.h
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sunserialcore.h
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sunxi-rsb.h
2.89
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superhyway.h
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surface_acpi_notify.h
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suspend.h
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svga.h
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swapops.h
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swiotlb.h
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switchtec.h
10.9
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sxgbe_platform.h
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sync_core.h
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sync_file.h
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synclink.h
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sys.h
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sys_soc.h
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syscalls.h
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syscore_ops.h
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sysctl.h
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sysfb.h
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sysfs.h
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sysrq.h
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sysv_fs.h
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t10-pi.h
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task_io_accounting_ops.h
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task_work.h
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taskstats_kern.h
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tboot.h
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tc.h
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tcp.h
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tee_drv.h
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textsearch.h
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textsearch_fsm.h
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tfrc.h
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thermal.h
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thread_info.h
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threads.h
1.28
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thunderbolt.h
20.78
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ti-emif-sram.h
5.15
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ti_wilink_st.h
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tick.h
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tifm.h
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timb_dma.h
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timb_gpio.h
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time.h
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time32.h
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time_namespace.h
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timecounter.h
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timekeeper_internal.h
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timekeeping.h
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timer.h
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timerfd.h
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timeriomem-rng.h
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timerqueue.h
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timex.h
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tnum.h
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topology.h
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torture.h
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toshiba.h
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tpm.h
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tpm_command.h
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tpm_eventlog.h
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trace.h
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trace_clock.h
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trace_seq.h
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tracefs.h
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tracehook.h
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tracepoint-defs.h
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tracepoint.h
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transport_class.h
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ts-nbus.h
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tsacct_kern.h
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tty.h
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tty_buffer.h
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tty_port.h
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typecheck.h
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types.h
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u64_stats_sync.h
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uaccess.h
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ucb1400.h
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ucs2_string.h
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udp.h
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uidgid.h
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uio_driver.h
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unicode.h
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units.h
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uprobes.h
6
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usb.h
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usb_usual.h
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usbdevice_fs.h
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user-return-notifier.h
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user.h
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user_namespace.h
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userfaultfd_k.h
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util_macros.h
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utsname.h
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uuid.h
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vbox_utils.h
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vdpa.h
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verification.h
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vermagic.h
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vfio.h
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vfio_pci_core.h
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vfs.h
116
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vga_switcheroo.h
8.62
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vgaarb.h
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vhost_iotlb.h
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via-core.h
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via.h
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6.7
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virtio_byteorder.h
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virtio_caif.h
513
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virtio_config.h
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virtio_console.h
1.93
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virtio_dma_buf.h
1.12
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virtio_net.h
5.38
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virtio_pci_modern.h
3.25
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virtio_ring.h
2.95
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virtio_vsock.h
4.79
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visorbus.h
12.23
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vlynq.h
3.22
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vm_event_item.h
3.46
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vmacache.h
722
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vmalloc.h
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vme.h
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vmpressure.h
1.68
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vmstat.h
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vmw_vmci_api.h
2.88
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vmw_vmci_defs.h
27.5
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vringh.h
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vt.h
611
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vt_buffer.h
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vt_kern.h
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vtime.h
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w1-gpio.h
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w1.h
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wait.h
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wait_bit.h
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watch_queue.h
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watchdog.h
8.21
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win_minmax.h
832
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wireless.h
1.4
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wkup_m3_ipc.h
1.75
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wl12xx.h
810
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wm97xx.h
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wmi.h
1.56
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Code Editor : clk-provider.h
/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> */ #ifndef __LINUX_CLK_PROVIDER_H #define __LINUX_CLK_PROVIDER_H #include <linux/of.h> #include <linux/of_clk.h> /* * flags used across common struct clk. these flags should only affect the * top-level framework. custom flags for dealing with hardware specifics * belong in struct clk_foo * * Please update clk_flags[] in drivers/clk/clk.c when making changes here! */ #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ /* unused */ /* unused */ #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ /* parents need enable during gate/ungate, set rate and re-parent */ #define CLK_OPS_PARENT_ENABLE BIT(12) /* duty cycle call may be forwarded to the parent clock */ #define CLK_DUTY_CYCLE_PARENT BIT(13) struct clk; struct clk_hw; struct clk_core; struct dentry; /** * struct clk_rate_request - Structure encoding the clk constraints that * a clock user might require. * * @rate: Requested clock rate. This field will be adjusted by * clock drivers according to hardware capabilities. * @min_rate: Minimum rate imposed by clk users. * @max_rate: Maximum rate imposed by clk users. * @best_parent_rate: The best parent rate a parent can provide to fulfill the * requested constraints. * @best_parent_hw: The most appropriate parent clock that fulfills the * requested constraints. * */ struct clk_rate_request { unsigned long rate; unsigned long min_rate; unsigned long max_rate; unsigned long best_parent_rate; struct clk_hw *best_parent_hw; }; /** * struct clk_duty - Struture encoding the duty cycle ratio of a clock * * @num: Numerator of the duty cycle ratio * @den: Denominator of the duty cycle ratio */ struct clk_duty { unsigned int num; unsigned int den; }; /** * struct clk_ops - Callback operations for hardware clocks; these are to * be provided by the clock implementation, and will be called by drivers * through the clk_* api. * * @prepare: Prepare the clock for enabling. This must not return until * the clock is fully prepared, and it's safe to call clk_enable. * This callback is intended to allow clock implementations to * do any initialisation that may sleep. Called with * prepare_lock held. * * @unprepare: Release the clock from its prepared state. This will typically * undo any work done in the @prepare callback. Called with * prepare_lock held. * * @is_prepared: Queries the hardware to determine if the clock is prepared. * This function is allowed to sleep. Optional, if this op is not * set then the prepare count will be used. * * @unprepare_unused: Unprepare the clock atomically. Only called from * clk_disable_unused for prepare clocks with special needs. * Called with prepare mutex held. This function may sleep. * * @enable: Enable the clock atomically. This must not return until the * clock is generating a valid clock signal, usable by consumer * devices. Called with enable_lock held. This function must not * sleep. * * @disable: Disable the clock atomically. Called with enable_lock held. * This function must not sleep. * * @is_enabled: Queries the hardware to determine if the clock is enabled. * This function must not sleep. Optional, if this op is not * set then the enable count will be used. * * @disable_unused: Disable the clock atomically. Only called from * clk_disable_unused for gate clocks with special needs. * Called with enable_lock held. This function must not * sleep. * * @save_context: Save the context of the clock in prepration for poweroff. * * @restore_context: Restore the context of the clock after a restoration * of power. * * @recalc_rate Recalculate the rate of this clock, by querying hardware. The * parent rate is an input parameter. It is up to the caller to * ensure that the prepare_mutex is held across this call. * Returns the calculated rate. Optional, but recommended - if * this op is not set then clock rate will be initialized to 0. * * @round_rate: Given a target rate as input, returns the closest rate actually * supported by the clock. The parent rate is an input/output * parameter. * * @determine_rate: Given a target rate as input, returns the closest rate * actually supported by the clock, and optionally the parent clock * that should be used to provide the clock rate. * * @set_parent: Change the input source of this clock; for clocks with multiple * possible parents specify a new parent by passing in the index * as a u8 corresponding to the parent in either the .parent_names * or .parents arrays. This function in affect translates an * array index into the value programmed into the hardware. * Returns 0 on success, -EERROR otherwise. * * @get_parent: Queries the hardware to determine the parent of a clock. The * return value is a u8 which specifies the index corresponding to * the parent clock. This index can be applied to either the * .parent_names or .parents arrays. In short, this function * translates the parent value read from hardware into an array * index. Currently only called when the clock is initialized by * __clk_init. This callback is mandatory for clocks with * multiple parents. It is optional (and unnecessary) for clocks * with 0 or 1 parents. * * @set_rate: Change the rate of this clock. The requested rate is specified * by the second argument, which should typically be the return * of .round_rate call. The third argument gives the parent rate * which is likely helpful for most .set_rate implementation. * Returns 0 on success, -EERROR otherwise. * * @set_rate_and_parent: Change the rate and the parent of this clock. The * requested rate is specified by the second argument, which * should typically be the return of .round_rate call. The * third argument gives the parent rate which is likely helpful * for most .set_rate_and_parent implementation. The fourth * argument gives the parent index. This callback is optional (and * unnecessary) for clocks with 0 or 1 parents as well as * for clocks that can tolerate switching the rate and the parent * separately via calls to .set_parent and .set_rate. * Returns 0 on success, -EERROR otherwise. * * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy * is expressed in ppb (parts per billion). The parent accuracy is * an input parameter. * Returns the calculated accuracy. Optional - if this op is not * set then clock accuracy will be initialized to parent accuracy * or 0 (perfect clock) if clock has no parent. * * @get_phase: Queries the hardware to get the current phase of a clock. * Returned values are 0-359 degrees on success, negative * error codes on failure. * * @set_phase: Shift the phase this clock signal in degrees specified * by the second argument. Valid values for degrees are * 0-359. Return 0 on success, otherwise -EERROR. * * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio * of a clock. Returned values denominator cannot be 0 and must be * superior or equal to the numerator. * * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by * the numerator (2nd argurment) and denominator (3rd argument). * Argument must be a valid ratio (denominator > 0 * and >= numerator) Return 0 on success, otherwise -EERROR. * * @init: Perform platform-specific initialization magic. * This is not used by any of the basic clock types. * This callback exist for HW which needs to perform some * initialisation magic for CCF to get an accurate view of the * clock. It may also be used dynamic resource allocation is * required. It shall not used to deal with clock parameters, * such as rate or parents. * Returns 0 on success, -EERROR otherwise. * * @terminate: Free any resource allocated by init. * * @debug_init: Set up type-specific debugfs entries for this clock. This * is called once, after the debugfs directory entry for this * clock has been created. The dentry pointer representing that * directory is provided as an argument. Called with * prepare_lock held. Returns 0 on success, -EERROR otherwise. * * * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow * implementations to split any work between atomic (enable) and sleepable * (prepare) contexts. If enabling a clock requires code that might sleep, * this must be done in clk_prepare. Clock enable code that will never be * called in a sleepable context may be implemented in clk_enable. * * Typically, drivers will call clk_prepare when a clock may be needed later * (eg. when a device is opened), and clk_enable when the clock is actually * required (eg. from an interrupt). Note that clk_prepare MUST have been * called before clk_enable. */ struct clk_ops { int (*prepare)(struct clk_hw *hw); void (*unprepare)(struct clk_hw *hw); int (*is_prepared)(struct clk_hw *hw); void (*unprepare_unused)(struct clk_hw *hw); int (*enable)(struct clk_hw *hw); void (*disable)(struct clk_hw *hw); int (*is_enabled)(struct clk_hw *hw); void (*disable_unused)(struct clk_hw *hw); int (*save_context)(struct clk_hw *hw); void (*restore_context)(struct clk_hw *hw); unsigned long (*recalc_rate)(struct clk_hw *hw, unsigned long parent_rate); long (*round_rate)(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate); int (*determine_rate)(struct clk_hw *hw, struct clk_rate_request *req); int (*set_parent)(struct clk_hw *hw, u8 index); u8 (*get_parent)(struct clk_hw *hw); int (*set_rate)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); int (*set_rate_and_parent)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index); unsigned long (*recalc_accuracy)(struct clk_hw *hw, unsigned long parent_accuracy); int (*get_phase)(struct clk_hw *hw); int (*set_phase)(struct clk_hw *hw, int degrees); int (*get_duty_cycle)(struct clk_hw *hw, struct clk_duty *duty); int (*set_duty_cycle)(struct clk_hw *hw, struct clk_duty *duty); int (*init)(struct clk_hw *hw); void (*terminate)(struct clk_hw *hw); void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); }; /** * struct clk_parent_data - clk parent information * @hw: parent clk_hw pointer (used for clk providers with internal clks) * @fw_name: parent name local to provider registering clk * @name: globally unique parent name (used as a fallback) * @index: parent index local to provider registering clk (if @fw_name absent) */ struct clk_parent_data { const struct clk_hw *hw; const char *fw_name; const char *name; int index; }; /** * struct clk_init_data - holds init data that's common to all clocks and is * shared between the clock provider and the common clock framework. * * @name: clock name * @ops: operations this clock supports * @parent_names: array of string names for all possible parents * @parent_data: array of parent data for all possible parents (when some * parents are external to the clk controller) * @parent_hws: array of pointers to all possible parents (when all parents * are internal to the clk controller) * @num_parents: number of possible parents * @flags: framework-level hints and quirks */ struct clk_init_data { const char *name; const struct clk_ops *ops; /* Only one of the following three should be assigned */ const char * const *parent_names; const struct clk_parent_data *parent_data; const struct clk_hw **parent_hws; u8 num_parents; unsigned long flags; }; /** * struct clk_hw - handle for traversing from a struct clk to its corresponding * hardware-specific structure. struct clk_hw should be declared within struct * clk_foo and then referenced by the struct clk instance that uses struct * clk_foo's clk_ops * * @core: pointer to the struct clk_core instance that points back to this * struct clk_hw instance * * @clk: pointer to the per-user struct clk instance that can be used to call * into the clk API * * @init: pointer to struct clk_init_data that contains the init data shared * with the common clock framework. This pointer will be set to NULL once * a clk_register() variant is called on this clk_hw pointer. */ struct clk_hw { struct clk_core *core; struct clk *clk; const struct clk_init_data *init; }; /* * DOC: Basic clock implementations common to many platforms * * Each basic clock hardware type is comprised of a structure describing the * clock hardware, implementations of the relevant callbacks in struct clk_ops, * unique flags for that hardware type, a registration function and an * alternative macro for static initialization */ /** * struct clk_fixed_rate - fixed-rate clock * @hw: handle between common and hardware-specific interfaces * @fixed_rate: constant frequency of clock * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion) * @flags: hardware specific flags * * Flags: * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk * instead of what's set in @fixed_accuracy. */ struct clk_fixed_rate { struct clk_hw hw; unsigned long fixed_rate; unsigned long fixed_accuracy; unsigned long flags; }; #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0) extern const struct clk_ops clk_fixed_rate_ops; struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, unsigned long fixed_rate, unsigned long fixed_accuracy, unsigned long clk_fixed_flags); struct clk *clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate); /** * clk_hw_register_fixed_rate - register fixed-rate clock with the clock * framework * @dev: device that is registering this clock * @name: name of this clock * @parent_name: name of clock's parent * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate */ #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \ NULL, (flags), (fixed_rate), 0, 0) /** * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with * the clock framework * @dev: device that is registering this clock * @name: name of this clock * @parent_hw: pointer to parent clk * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate */ #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \ fixed_rate) \ __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \ NULL, (flags), (fixed_rate), 0, 0) /** * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with * the clock framework * @dev: device that is registering this clock * @name: name of this clock * @parent_data: parent clk data * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate */ #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \ fixed_rate) \ __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ (parent_data), (flags), (fixed_rate), 0, \ 0) /** * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with * the clock framework * @dev: device that is registering this clock * @name: name of this clock * @parent_name: name of clock's parent * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate * @fixed_accuracy: non-adjustable clock accuracy */ #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \ flags, fixed_rate, \ fixed_accuracy) \ __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \ NULL, NULL, (flags), (fixed_rate), \ (fixed_accuracy), 0) /** * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate * clock with the clock framework * @dev: device that is registering this clock * @name: name of this clock * @parent_hw: pointer to parent clk * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate * @fixed_accuracy: non-adjustable clock accuracy */ #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \ parent_hw, flags, fixed_rate, fixed_accuracy) \ __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \ NULL, NULL, (flags), (fixed_rate), \ (fixed_accuracy), 0) /** * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate * clock with the clock framework * @dev: device that is registering this clock * @name: name of this clock * @parent_name: name of clock's parent * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate * @fixed_accuracy: non-adjustable clock accuracy */ #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \ parent_data, flags, fixed_rate, fixed_accuracy) \ __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ (parent_data), NULL, (flags), \ (fixed_rate), (fixed_accuracy), 0) void clk_unregister_fixed_rate(struct clk *clk); void clk_hw_unregister_fixed_rate(struct clk_hw *hw); void of_fixed_clk_setup(struct device_node *np); /** * struct clk_gate - gating clock * * @hw: handle between common and hardware-specific interfaces * @reg: register controlling gate * @bit_idx: single bit controlling gate * @flags: hardware-specific flags * @lock: register lock * * Clock which can gate its output. Implements .enable & .disable * * Flags: * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to * enable the clock. Setting this flag does the opposite: setting the bit * disable the clock and clearing it enables the clock * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit * of this register, and mask of gate bits are in higher 16-bit of this * register. While setting the gate bits, higher 16-bit should also be * updated to indicate changing gate bits. * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for * the gate register. Setting this flag makes the register accesses big * endian. */ struct clk_gate { struct clk_hw hw; void __iomem *reg; u8 bit_idx; u8 flags; spinlock_t *lock; }; #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) #define CLK_GATE_SET_TO_DISABLE BIT(0) #define CLK_GATE_HIWORD_MASK BIT(1) #define CLK_GATE_BIG_ENDIAN BIT(2) extern const struct clk_ops clk_gate_ops; struct clk_hw *__clk_hw_register_gate(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); struct clk *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); /** * clk_hw_register_gate - register a gate clock with the clock framework * @dev: device that is registering this clock * @name: name of this clock * @parent_name: name of this clock's parent * @flags: framework-specific flags for this clock * @reg: register address to control gating of this clock * @bit_idx: which bit in the register controls gating of this clock * @clk_gate_flags: gate-specific flags for this clock * @lock: shared register lock for this clock */ #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \ clk_gate_flags, lock) \ __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ NULL, (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) /** * clk_hw_register_gate_parent_hw - register a gate clock with the clock * framework * @dev: device that is registering this clock * @name: name of this clock * @parent_hw: pointer to parent clk * @flags: framework-specific flags for this clock * @reg: register address to control gating of this clock * @bit_idx: which bit in the register controls gating of this clock * @clk_gate_flags: gate-specific flags for this clock * @lock: shared register lock for this clock */ #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \ bit_idx, clk_gate_flags, lock) \ __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ NULL, (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) /** * clk_hw_register_gate_parent_data - register a gate clock with the clock * framework * @dev: device that is registering this clock * @name: name of this clock * @parent_data: parent clk data * @flags: framework-specific flags for this clock * @reg: register address to control gating of this clock * @bit_idx: which bit in the register controls gating of this clock * @clk_gate_flags: gate-specific flags for this clock * @lock: shared register lock for this clock */ #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \ bit_idx, clk_gate_flags, lock) \ __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \ (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) void clk_unregister_gate(struct clk *clk); void clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct clk_hw *hw); struct clk_div_table { unsigned int val; unsigned int div; }; /** * struct clk_divider - adjustable divider clock * * @hw: handle between common and hardware-specific interfaces * @reg: register containing the divider * @shift: shift to the divider bit field * @width: width of the divider bit field * @table: array of value/divider pairs, last entry should have div = 0 * @lock: register lock * * Clock with an adjustable divider affecting its output frequency. Implements * .recalc_rate, .set_rate and .round_rate * * Flags: * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is * the raw value read from the register, with the value of zero considered * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from * the hardware register * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. * Some hardware implementations gracefully handle this case and allow a * zero divisor by not modifying their input clock * (divide by one / bypass). * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit * of this register, and mask of divider bits are in higher 16-bit of this * register. While setting the divider bits, higher 16-bit should also be * updated to indicate changing divider bits. * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded * to the closest integer instead of the up one. * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should * not be changed by the clock framework. * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED * except when the value read from the register is zero, the divisor is * 2^width of the field. * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used * for the divider register. Setting this flag makes the register accesses * big endian. */ struct clk_divider { struct clk_hw hw; void __iomem *reg; u8 shift; u8 width; u8 flags; const struct clk_div_table *table; spinlock_t *lock; }; #define clk_div_mask(width) ((1 << (width)) - 1) #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) #define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_POWER_OF_TWO BIT(1) #define CLK_DIVIDER_ALLOW_ZERO BIT(2) #define CLK_DIVIDER_HIWORD_MASK BIT(3) #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) #define CLK_DIVIDER_READ_ONLY BIT(5) #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) #define CLK_DIVIDER_BIG_ENDIAN BIT(7) extern const struct clk_ops clk_divider_ops; extern const struct clk_ops clk_divider_ro_ops; unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, unsigned int val, const struct clk_div_table *table, unsigned long flags, unsigned long width); long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags); long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags, unsigned int val); int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, const struct clk_div_table *table, u8 width, unsigned long flags); int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, const struct clk_div_table *table, u8 width, unsigned long flags, unsigned int val); int divider_get_val(unsigned long rate, unsigned long parent_rate, const struct clk_div_table *table, u8 width, unsigned long flags); struct clk_hw *__clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); struct clk_hw *__devm_clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); struct clk *clk_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); /** * clk_register_divider - register a divider clock with the clock framework * @dev: device registering this clock * @name: name of this clock * @parent_name: name of clock's parent * @flags: framework-specific flags * @reg: register address to adjust divider * @shift: number of bits to shift the bitfield * @width: width of the bitfield * @clk_divider_flags: divider-specific flags for this clock * @lock: shared register lock for this clock */ #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \ clk_divider_flags, lock) \ clk_register_divider_table((dev), (name), (parent_name), (flags), \ (reg), (shift), (width), \ (clk_divider_flags), NULL, (lock)) /** * clk_hw_register_divider - register a divider clock with the clock framework * @dev: device registering this clock * @name: name of this clock * @parent_name: name of clock's parent * @flags: framework-specific flags * @reg: register address to adjust divider * @shift: number of bits to shift the bitfield * @width: width of the bitfield * @clk_divider_flags: divider-specific flags for this clock * @lock: shared register lock for this clock */ #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ width, clk_divider_flags, lock) \ __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ NULL, (flags), (reg), (shift), (width), \ (clk_divider_flags), NULL, (lock)) /** * clk_hw_register_divider_parent_hw - register a divider clock with the clock * framework * @dev: device registering this clock * @name: name of this clock * @parent_hw: pointer to parent clk * @flags: framework-specific flags * @reg: register address to adjust divider * @shift: number of bits to shift the bitfield * @width: width of the bitfield * @clk_divider_flags: divider-specific flags for this clock * @lock: shared register lock for this clock */ #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \ shift, width, clk_divider_flags, \ lock) \ __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ NULL, (flags), (reg), (shift), (width), \ (clk_divider_flags), NULL, (lock)) /** * clk_hw_register_divider_parent_data - register a divider clock with the clock * framework * @dev: device registering this clock * @name: name of this clock * @parent_data: parent clk data * @flags: framework-specific flags * @reg: register address to adjust divider * @shift: number of bits to shift the bitfield * @width: width of the bitfield * @clk_divider_flags: divider-specific flags for this clock * @lock: shared register lock for this clock */ #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \ reg, shift, width, \ clk_divider_flags, lock) \ __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ (parent_data), (flags), (reg), (shift), \ (width), (clk_divider_flags), NULL, (lock)) /** * clk_hw_register_divider_table - register a table based divider clock with * the clock framework * @dev: device registering this clock * @name: name of this clock * @parent_name: name of clock's parent * @flags: framework-specific flags * @reg: register address to adjust divider * @shift: number of bits to shift the bitfield * @width: width of the bitfield * @clk_divider_flags: divider-specific flags for this clock * @table: array of divider/value pairs ending with a div set to 0 * @lock: shared register lock for this clock */ #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \ shift, width, clk_divider_flags, table, \ lock) \ __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ NULL, (flags), (reg), (shift), (width), \ (clk_divider_flags), (table), (lock)) /** * clk_hw_register_divider_table_parent_hw - register a table based divider * clock with the clock framework * @dev: device registering this clock * @name: name of this clock * @parent_hw: pointer to parent clk * @flags: framework-specific flags * @reg: register address to adjust divider * @shift: number of bits to shift the bitfield * @width: width of the bitfield * @clk_divider_flags: divider-specific flags for this clock * @table: array of divider/value pairs ending with a div set to 0 * @lock: shared register lock for this clock */ #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \ reg, shift, width, \ clk_divider_flags, table, \ lock) \ __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ NULL, (flags), (reg), (shift), (width), \ (clk_divider_flags), (table), (lock)) /** * clk_hw_register_divider_table_parent_data - register a table based divider * clock with the clock framework * @dev: device registering this clock * @name: name of this clock * @parent_data: parent clk data * @flags: framework-specific flags * @reg: register address to adjust divider * @shift: number of bits to shift the bitfield * @width: width of the bitfield * @clk_divider_flags: divider-specific flags for this clock * @table: array of divider/value pairs ending with a div set to 0 * @lock: shared register lock for this clock */ #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \ flags, reg, shift, width, \ clk_divider_flags, table, \ lock) \ __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ (parent_data), (flags), (reg), (shift), \ (width), (clk_divider_flags), (table), \ (lock)) /** * devm_clk_hw_register_divider - register a divider clock with the clock framework * @dev: device registering this clock * @name: name of this clock * @parent_name: name of clock's parent * @flags: framework-specific flags * @reg: register address to adjust divider * @shift: number of bits to shift the bitfield * @width: width of the bitfield * @clk_divider_flags: divider-specific flags for this clock * @lock: shared register lock for this clock */ #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ width, clk_divider_flags, lock) \ __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ NULL, (flags), (reg), (shift), (width), \ (clk_divider_flags), NULL, (lock)) /** * devm_clk_hw_register_divider_table - register a table based divider clock * with the clock framework (devres variant) * @dev: device registering this clock * @name: name of this clock * @parent_name: name of clock's parent * @flags: framework-specific flags * @reg: register address to adjust divider * @shift: number of bits to shift the bitfield * @width: width of the bitfield * @clk_divider_flags: divider-specific flags for this clock * @table: array of divider/value pairs ending with a div set to 0 * @lock: shared register lock for this clock */ #define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \ reg, shift, width, \ clk_divider_flags, table, lock) \ __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \ NULL, NULL, (flags), (reg), (shift), \ (width), (clk_divider_flags), (table), \ (lock)) void clk_unregister_divider(struct clk *clk); void clk_hw_unregister_divider(struct clk_hw *hw); /** * struct clk_mux - multiplexer clock * * @hw: handle between common and hardware-specific interfaces * @reg: register controlling multiplexer * @table: array of register values corresponding to the parent index * @shift: shift to multiplexer bit field * @mask: mask of mutliplexer bit field * @flags: hardware-specific flags * @lock: register lock * * Clock with multiple selectable parents. Implements .get_parent, .set_parent * and .recalc_rate * * Flags: * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this * register, and mask of mux bits are in higher 16-bit of this register. * While setting the mux bits, higher 16-bit should also be updated to * indicate changing mux bits. * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the * .get_parent clk_op. * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired * frequency. * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for * the mux register. Setting this flag makes the register accesses big * endian. */ struct clk_mux { struct clk_hw hw; void __iomem *reg; u32 *table; u32 mask; u8 shift; u8 flags; spinlock_t *lock; }; #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) #define CLK_MUX_INDEX_ONE BIT(0) #define CLK_MUX_INDEX_BIT BIT(1) #define CLK_MUX_HIWORD_MASK BIT(2) #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ #define CLK_MUX_ROUND_CLOSEST BIT(4) #define CLK_MUX_BIG_ENDIAN BIT(5) extern const struct clk_ops clk_mux_ops; extern const struct clk_ops clk_mux_ro_ops; struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, const char *name, u8 num_parents, const char * const *parent_names, const struct clk_hw **parent_hws, const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock); struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np, const char *name, u8 num_parents, const char * const *parent_names, const struct clk_hw **parent_hws, const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock); struct clk *clk_register_mux_table(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock); #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \ shift, width, clk_mux_flags, lock) \ clk_register_mux_table((dev), (name), (parent_names), (num_parents), \ (flags), (reg), (shift), BIT((width)) - 1, \ (clk_mux_flags), NULL, (lock)) #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \ flags, reg, shift, mask, clk_mux_flags, \ table, lock) \ __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ (parent_names), NULL, NULL, (flags), (reg), \ (shift), (mask), (clk_mux_flags), (table), \ (lock)) #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ shift, width, clk_mux_flags, lock) \ __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ (parent_names), NULL, NULL, (flags), (reg), \ (shift), BIT((width)) - 1, (clk_mux_flags), \ NULL, (lock)) #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \ reg, shift, width, clk_mux_flags, lock) \ __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ (parent_hws), NULL, (flags), (reg), (shift), \ BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \ flags, reg, shift, width, \ clk_mux_flags, lock) \ __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ (parent_data), (flags), (reg), (shift), \ BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ shift, width, clk_mux_flags, lock) \ __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \ (parent_names), NULL, NULL, (flags), (reg), \ (shift), BIT((width)) - 1, (clk_mux_flags), \ NULL, (lock)) int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, unsigned int val); unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index); void clk_unregister_mux(struct clk *clk); void clk_hw_unregister_mux(struct clk_hw *hw); void of_fixed_factor_clk_setup(struct device_node *node); /** * struct clk_fixed_factor - fixed multiplier and divider clock * * @hw: handle between common and hardware-specific interfaces * @mult: multiplier * @div: divider * * Clock with a fixed multiplier and divider. The output frequency is the * parent clock rate divided by div and multiplied by mult. * Implements .recalc_rate, .set_rate and .round_rate */ struct clk_fixed_factor { struct clk_hw hw; unsigned int mult; unsigned int div; }; #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) extern const struct clk_ops clk_fixed_factor_ops; struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); void clk_unregister_fixed_factor(struct clk *clk); struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); /** * struct clk_fractional_divider - adjustable fractional divider clock * * @hw: handle between common and hardware-specific interfaces * @reg: register containing the divider * @mshift: shift to the numerator bit field * @mwidth: width of the numerator bit field * @nshift: shift to the denominator bit field * @nwidth: width of the denominator bit field * @lock: register lock * * Clock with adjustable fractional divider affecting its output frequency. * * Flags: * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED * is set then the numerator and denominator are both the value read * plus one. * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are * used for the divider register. Setting this flag makes the register * accesses big endian. * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might * be saturated and the caller will get quite far from the good enough * approximation. Instead the caller may require, by setting this flag, * to shift left by a few bits in case, when the asked one is quite small * to satisfy the desired range of denominator. It assumes that on the * caller's side the power-of-two capable prescaler exists. */ struct clk_fractional_divider { struct clk_hw hw; void __iomem *reg; u8 mshift; u8 mwidth; u32 mmask; u8 nshift; u8 nwidth; u32 nmask; u8 flags; void (*approximation)(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate, unsigned long *m, unsigned long *n); spinlock_t *lock; }; #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) #define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2) struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, u8 clk_divider_flags, spinlock_t *lock); struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, u8 clk_divider_flags, spinlock_t *lock); void clk_hw_unregister_fractional_divider(struct clk_hw *hw); /** * struct clk_multiplier - adjustable multiplier clock * * @hw: handle between common and hardware-specific interfaces * @reg: register containing the multiplier * @shift: shift to the multiplier bit field * @width: width of the multiplier bit field * @lock: register lock * * Clock with an adjustable multiplier affecting its output frequency. * Implements .recalc_rate, .set_rate and .round_rate * * Flags: * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read * from the register, with 0 being a valid value effectively * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is * set, then a null multiplier will be considered as a bypass, * leaving the parent rate unmodified. * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be * rounded to the closest integer instead of the down one. * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are * used for the multiplier register. Setting this flag makes the register * accesses big endian. */ struct clk_multiplier { struct clk_hw hw; void __iomem *reg; u8 shift; u8 width; u8 flags; spinlock_t *lock; }; #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2) extern const struct clk_ops clk_multiplier_ops; /*** * struct clk_composite - aggregate clock of mux, divider and gate clocks * * @hw: handle between common and hardware-specific interfaces * @mux_hw: handle between composite and hardware-specific mux clock * @rate_hw: handle between composite and hardware-specific rate clock * @gate_hw: handle between composite and hardware-specific gate clock * @mux_ops: clock ops for mux * @rate_ops: clock ops for rate * @gate_ops: clock ops for gate */ struct clk_composite { struct clk_hw hw; struct clk_ops ops; struct clk_hw *mux_hw; struct clk_hw *rate_hw; struct clk_hw *gate_hw; const struct clk_ops *mux_ops; const struct clk_ops *rate_ops; const struct clk_ops *gate_ops; }; #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) struct clk *clk_register_composite(struct device *dev, const char *name, const char * const *parent_names, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags); struct clk *clk_register_composite_pdata(struct device *dev, const char *name, const struct clk_parent_data *parent_data, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags); void clk_unregister_composite(struct clk *clk); struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, const char * const *parent_names, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags); struct clk_hw *clk_hw_register_composite_pdata(struct device *dev, const char *name, const struct clk_parent_data *parent_data, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags); struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev, const char *name, const struct clk_parent_data *parent_data, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags); void clk_hw_unregister_composite(struct clk_hw *hw); struct clk *clk_register(struct device *dev, struct clk_hw *hw); struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw); void clk_unregister(struct clk *clk); void devm_clk_unregister(struct device *dev, struct clk *clk); void clk_hw_unregister(struct clk_hw *hw); void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw); /* helper functions */ const char *__clk_get_name(const struct clk *clk); const char *clk_hw_get_name(const struct clk_hw *hw); #ifdef CONFIG_COMMON_CLK struct clk_hw *__clk_get_hw(struct clk *clk); #else static inline struct clk_hw *__clk_get_hw(struct clk *clk) { return (struct clk_hw *)clk; } #endif struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id); struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw, const char *con_id); unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index); int clk_hw_get_parent_index(struct clk_hw *hw); int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); unsigned int __clk_get_enable_count(struct clk *clk); unsigned long clk_hw_get_rate(const struct clk_hw *hw); unsigned long clk_hw_get_flags(const struct clk_hw *hw); #define clk_hw_can_set_rate_parent(hw) \ (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT) bool clk_hw_is_prepared(const struct clk_hw *hw); bool clk_hw_rate_is_protected(const struct clk_hw *hw); bool clk_hw_is_enabled(const struct clk_hw *hw); bool __clk_is_enabled(struct clk *clk); struct clk *__clk_lookup(const char *name); int __clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req); int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); int __clk_mux_determine_rate_closest(struct clk_hw *hw, struct clk_rate_request *req); int clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req, unsigned long flags); void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, unsigned long max_rate); static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) { dst->clk = src->clk; dst->core = src->core; } static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags) { return divider_round_rate_parent(hw, clk_hw_get_parent(hw), rate, prate, table, width, flags); } static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags, unsigned int val) { return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), rate, prate, table, width, flags, val); } /* * FIXME clock api without lock protection */ unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); struct clk_onecell_data { struct clk **clks; unsigned int clk_num; }; struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) /* * Use this macro when you have a driver that requires two initialization * routines, one at of_clk_init(), and one at platform device probe */ #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ static void __init name##_of_clk_init_driver(struct device_node *np) \ { \ of_node_clear_flag(np, OF_POPULATED); \ fn(np); \ } \ OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_names = (const char *[]) { _parent }, \ .num_parents = 1, \ .ops = _ops, \ }) #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_hws = (const struct clk_hw*[]) { _parent }, \ .num_parents = 1, \ .ops = _ops, \ }) /* * This macro is intended for drivers to be able to share the otherwise * individual struct clk_hw[] compound literals created by the compiler * when using CLK_HW_INIT_HW. It does NOT support multiple parents. */ #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_hws = _parent, \ .num_parents = 1, \ .ops = _ops, \ }) #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_data = (const struct clk_parent_data[]) { \ { .fw_name = _parent }, \ }, \ .num_parents = 1, \ .ops = _ops, \ }) #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_names = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ .ops = _ops, \ }) #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_hws = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ .ops = _ops, \ }) #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_data = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ .ops = _ops, \ }) #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_names = NULL, \ .num_parents = 0, \ .ops = _ops, \ }) #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ _div, _mult, _flags) \ struct clk_fixed_factor _struct = { \ .div = _div, \ .mult = _mult, \ .hw.init = CLK_HW_INIT(_name, \ _parent, \ &clk_fixed_factor_ops, \ _flags), \ } #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \ _div, _mult, _flags) \ struct clk_fixed_factor _struct = { \ .div = _div, \ .mult = _mult, \ .hw.init = CLK_HW_INIT_HW(_name, \ _parent, \ &clk_fixed_factor_ops, \ _flags), \ } /* * This macro allows the driver to reuse the _parent array for multiple * fixed factor clk declarations. */ #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \ _div, _mult, _flags) \ struct clk_fixed_factor _struct = { \ .div = _div, \ .mult = _mult, \ .hw.init = CLK_HW_INIT_HWS(_name, \ _parent, \ &clk_fixed_factor_ops, \ _flags), \ } #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \ _div, _mult, _flags) \ struct clk_fixed_factor _struct = { \ .div = _div, \ .mult = _mult, \ .hw.init = CLK_HW_INIT_FW_NAME(_name, \ _parent, \ &clk_fixed_factor_ops, \ _flags), \ } #ifdef CONFIG_OF int of_clk_add_provider(struct device_node *np, struct clk *(*clk_src_get)(struct of_phandle_args *args, void *data), void *data); int of_clk_add_hw_provider(struct device_node *np, struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data), void *data); int devm_of_clk_add_hw_provider(struct device *dev, struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data), void *data); void of_clk_del_provider(struct device_node *np); void devm_of_clk_del_provider(struct device *dev); struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, void *data); struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data); struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data); int of_clk_parent_fill(struct device_node *np, const char **parents, unsigned int size); int of_clk_detect_critical(struct device_node *np, int index, unsigned long *flags); #else /* !CONFIG_OF */ static inline int of_clk_add_provider(struct device_node *np, struct clk *(*clk_src_get)(struct of_phandle_args *args, void *data), void *data) { return 0; } static inline int of_clk_add_hw_provider(struct device_node *np, struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data), void *data) { return 0; } static inline int devm_of_clk_add_hw_provider(struct device *dev, struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data), void *data) { return 0; } static inline void of_clk_del_provider(struct device_node *np) {} static inline void devm_of_clk_del_provider(struct device *dev) {} static inline struct clk *of_clk_src_simple_get( struct of_phandle_args *clkspec, void *data) { return ERR_PTR(-ENOENT); } static inline struct clk_hw * of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) { return ERR_PTR(-ENOENT); } static inline struct clk *of_clk_src_onecell_get( struct of_phandle_args *clkspec, void *data) { return ERR_PTR(-ENOENT); } static inline struct clk_hw * of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) { return ERR_PTR(-ENOENT); } static inline int of_clk_parent_fill(struct device_node *np, const char **parents, unsigned int size) { return 0; } static inline int of_clk_detect_critical(struct device_node *np, int index, unsigned long *flags) { return 0; } #endif /* CONFIG_OF */ void clk_gate_restore_context(struct clk_hw *hw); #endif /* CLK_PROVIDER_H */
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